High integration of semiconductor devices has been progressed year after year. Heretofore, fine processing techniques for reduction of circuit line widths have been developed because there is a need to increase the number of semiconductor elements integrated per unit area for the purpose of increasing the integration of the semiconductor devices. It has however been pointed out that malfunctions increase when fine processing of semiconductor devices proceeds excessively.
Under such circumstances, there have recently been developed three-dimensional structural semiconductor devices in which structural elements are arranged in directions parallel and perpendicular to substrate surfaces (see Patent Document 1). In the three-dimensional structural semiconductor device, the structural elements are arranged on the substrate of e.g. single crystal silicon not only in the direction parallel to the substrate surface as in conventional techniques but also in the direction perpendicular to the substrate surface by alternately laminating silicon electrode films and insulating films in plural layers on the substrate, subjecting the resulting laminated film to anisotropic etching such as reactive ion etching so as to form a plurality of fine holes or grooves of the order of 20 to 200 nm through the laminated film, and then, processing the shapes of parts of any specific layers (e.g. silicon electrode layers) appearing on inner surfaces of the holes or grooves For examples, it has been reported to manufacture large-capacity BiCS memories by plasma etching BiCS memory holes through Si electrode layers and silicon oxide insulating layers.
The specific layers appearing on the inner surfaces of the holes need to be processed by etching treat so as to impart the functionality of capacitors or transistors. There are known, as such etching treatment, a wet etching process using a liquid medicine having selective reaction characteristics against the specific layers and a dry etching process using a gas having selective reaction characteristics against the specific layers.
In the case of dry etching of silicon layers appearing on inner surfaces of fine holes in a three-dimensional structural element, the etching needs to be performed in a direction parallel to substrate surface. For such etching treatment, it is common practice to use ClF3 or XeF2 gas capable of isotropic etching (see Non-Patent Document 2).